Time-to-digital converter (TDC) with sub-ps-level resolution using current DAC and digitally controllable load capacitor

Abstract

This paper describes a cyclic time domain successive approximation (CTDSA) architecture that can be used as an interpolator in a time-to-digital converter (TDC). The new architecture of the CTDSA achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range. The propagation delay adjustment is implemented by digitally controlling both the unit load capacitors and the discharge current of the load capacitance using current DAC. The proposed CTDSA achieves 610 fs resolution and ∼2.5 ns dynamic range. The total simulated power consumption is 25.8mW with 5 MHz conversion rate with 3 V supply. The design was simulated using a 0.35 μm CMOS process.