VAIL: Variation-aware issue logic and performance binning for processor yield and profit improvement

Abstract

With increasing parameter variations, functional units (FUs) in a chip experience considerable local variations in maximum operating frequency. Effect of such within-die variations in a superscalar processor if addressed by worst-case frequency assignment, results in overly pessimistic yield in high-frequency bins. In this paper, we propose VAIL - a novel low-overhead instruction scheduling strategy that assigns best-case frequency by issuing the narrow-width (NW) operations to slower units. This exploits the abundance of NW operations (>70%) in a typical program and the fact that the critical path in FUs are not activated for these operations. Compared to existing varicycle approach, the proposed scheme demonstrates a large improvement in yield (∼ 27% at highest performance bin) and profit (10-15%) for a set of benchmark applications. It also improves the thermal profile for the FUs. Finally, it provides large opportunistic power saving (∼ 43%) in the slow units using supply gating of inactive bit-slices. Copyright 2010 ACM.