Variability aware modeling of socs: From device variations to manufactured system yield

Abstract

As CMOS technology feature sizes decrease, random within-die and inter-die process variations more and more jeopardize SoC parametric and functional yield. Largely neglected in the State-Of-the-Art, dynamic energy con-sumption and power dissipation becomes heavily a ected. This paper describes a technique to systematically bring statistically correlated timing energy variations all the way up from the device to the Soc level. We propose a ow for Variability Aware Modeling (VAM) and apply it to a case study using a industrial test vehicle. © 2009 IEEE.