The Virtex-5 Routing and Logic Architecture

Abstract

This report presents the architecture of Xilinx Virtex-5 – the first FPGA device fabricated at the at the 65 nm technology node. Switching from 90 nm to 65 nm enables a better output, higher density (the number of LEs in a single chip) and reduced energy consumption. Meanwhile, due to the increased logic density and the conducting architecture inherited from the previous preceding Virtex-4 generation of devices, the necessary overall length of the connecting wires is now considerably greater. Hence, there is a need of an improved connecting architecture for routing.