Delay Minimization in on Chip Interconnects by the Method of Logical Effort

Abstract

The ultimate aim of the work is to minimize the delay in on-chip interconnects. Our objective is to analyze the wire geometry impact for delay minimization. Here proposed effect is achieved by Logical effort(LE).The analyzes which is on the low swing where it was implemented by using CMOS circuit in 90 nm GPDK library and simulations on the cadence virtuoso ADE EDA tools. Once by reducing the delay the application is oriented for high speed applications. The logical effort (LE) model which reduces the delay minimization. This work which compensates both the long interconnects and short interconnects.