Stability analysis of sub-threshold 6t SRAM cell at 45 nm for iot application

Abstract

In ultra-Low power application the supply volt-age in the circuit is as minimum as possible to correct perform the operation. Reducing the supply voltage below the threshold Voltage of transistor is known as sub threshold voltage that affects the delay as well as stability parameter of the Circuit. In this paper body biased technique is applied at standard 6T SRAM which improve the static Current Noise Margin(SINM) and Write trip Current by the factor of 4.15 times and 4.7 times respectively from the Conventional (conv) 6T SRAM. SINM defined the read stability whereas WTI are write ability Parameters of the circuit. In the Sub threshold region delay parameter of the circuit increased, but in this paper delay and power of the proposed circuit are going to be degrades 2.34 times and 4.39 times from the conv. 6T SRAM at different Process Corner i.e. the Performance of the device get increased. In this paper conventional (Conv.)6T and Proposed(PP) 6T both have same W/L ratio at supply voltage of 400mv.