Physical Scaling Limits of FinFET Structure: A Simulation Study

Abstract

In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and Triple Gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively. To analyze the scaling limits of FinFET structure, simulations are performed using three variables: fin-thickness, fin-height and gate-length. From 2D simulation of DG FinFET, it is found that the gate-length (L) and fin-thickness (T fin) ratio plays a key role while deciding the performance of the device. Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS) increase abruptly when (L/T fin) ratio goes below 1.5. So, there will be a trade-off in between SCEs and on-current of the device since on-off current ratio is found to be high at small dimensions. From 3D simulation study on TG FinFET, It is found that both fin-thickness (T fin) and fin-height (H fin) can control the SCEs. However, T fin is found to be more dominant parameter than H fin while deciding the SCEs. DIBL and SS increase as (L eff /T fin) ratio decreases. The (L eff /T fin) ratio can be reduced below 1.5 unlike DG FinFET for the same SCEs. However, as this ratio approaches to 1, the SCEs can go beyond acceptable limits for TG FinFET structure. The relative ratio of H fin and T fin should be maximum at a given T fin and L eff to get maximum on-current per unit width. However, increasing H fin degrades the fin stability and degrades SCEs.