FPGA implementation of GPS location based secured data accessing system

Abstract

Now a day’s Field Programmable Gated Array (FPGA) are advanced architectures for various cryptographic systems and algorithm applications. Due to the reprogrammable flexibility of FPGAs, the advanced cryptographic algorithms are exploited to achieve high throughputs at the expense of very low chip area. The security can be improved by using standardized and proven-secure block ciphers like advanced encryption standard (AES). In this paper, we had designed our hardware optimization strategies for AES for high-speed, low-power algorithm for IoT applications with multiple levels of security. Main objective of action includes having user location data in the form of latitude/longitude followed by incorporating that with a randomly generated key for encryption. Receiver can only access the data of the host system and decrypt the cipher text only if the location coordinates and keys are matched.