Design and evaluation of a 32-bit carry select adder using 4-bit hybrid cla adder

Abstract

Adder circuits play a remarkable role in modern microprocessor. Adders are widely used in critical paths of arithmetic operation such as multiplication and subtraction. A Carry Select Adder (CSA) design methodology using a modified 4-bit Carry Look-Ahead (CLA) Adder has been proposed in this research. The proposed 4-bit CLA used hybrid logic style based logic circuits for Carry Generate (Gi) and Carry Propagate (Pi) functions in order to improve performance and reduce the number of transistors required. The modified 4-bit CLA is introduced as the basic unit for implementation of 32-bit CSA. The proposed design of hybrid CLA based 32-bit CSA has been compared with conventional static CMOS based 32-bit CSA and 32-bit Ripple Cary Adder (RCA) by conducting simulation using Cadence Virtuoso tools. Power consumption and delay in the proposed 32-bit CSA are found as 322.6 μW and 0.556 ns whereas those parameters in the conventional 32-bit CSA were 455.4 μW and 0.667 ns respectively. We have done all the simulation using Cadence Virtuoso 90 nm technology library.