A programmable built-in self-test core for embedded memories

Abstract

Testing embedded memories is becoming an industry-wide concern with the advent of deep-submicron technology and system-on-chip applications. We present a prototype chip for a programmable built-in self-test (BIST) design that is used for testing embedded memories, especially DRAMs. The BIST chip supports various memory test algorithms by a novel controller and sequencer design. The area of the core circuit is about 1,020 × 1,020μm2 using a 0.6μm CMOS process, and the clock speed is over 100MHz. © 2000 IEEE.