Performance tuning and analysis for stencil-based applications on POWER8 processor

Abstract

This article demonstrates an approach for combining general tuning techniques with the POWER8 hardware architecture through optimizing three representative stencil benchmarks. Two typical real-world applications, with kernels similar to those of the winning programs of the Gordon Bell Prize 2016 and 2017, are employed to illustrate algorithm modifcations and a combination of hardware-oriented tuning strategies with the application algorithms. This work flls the gap between hardware capability and software performance of the POWER8 processor, and provides useful guidance for optimizing stencil-based scientifc applications on POWER systems.