High- speed domino logic design

Abstract

Optimized standard CMOS-domino logic to a low cost logic and high speed design is presented. This paper combines a footless dynamic circuit with a robust self-timed inverted clocking scheme, a serial transistor is removed and capacitances at the output node are reduced in the new structures. This can be highly upgrade the operation speed of the circuit with very low power dissipation. Parametric simulation in Microwind 2 shows that over 20% performances enhancement is achieved. However, there are always the tradeoffs in designing high speed CMOS circuit and certain design issues need to be catered. CMOS-domino logic has been believed to gain its popularity in application of desktop computer and mobile devices in near future. © 2005 IEEE.