Duckcore: A fault‐tolerant processor core architecture based on the risc‐v isa

Abstract

With the development of large‐scale CMOS‐integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a fault‐tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC‐V. This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real‐time through the Supervision unit, and takes instruction rollbacks for different error types, which not only saves resources but also improves the reliability of the processor core. In the implementation process, all error injection tests are passed to verify the completeness of the function. In order to better verify the performance of the processor under different error intensity injections, the software is used to inject errors, the running program is run on the FPGA (Field Programmable Gate Array), and the impact of the actual radiation environment on the architecture is evaluated through the results. The architecture is applied to three–five‐stage open‐source processor cores and the results show that this method consumes fewer resources and its discrete design makes it more portable.