Low-power and metallic-CNT-tolerant CNTFET SRAM design

Abstract

For the past four decades, CMOS scaling has offered improved performance from one technology node to the next. However, as device scaling moves beyond the 32 nm node, significant technological challenges will be faced. Currently, two of the main challenges are the considerable increase of standby power dissipation and the increasing variability in device characteristics, which in turn affect the circuit and system reliability. The aforementioned challenges will become more prominent as CMOS scaling approaches atomic and quantum-mechanical physics boundaries [1].