Robust SRAM design via BIST-Assisted Timing-Tracking (BATT)

Abstract

A BIST-Assisted Timing-Tracking (BATT) scheme is proposed in this paper to facilitate robust read operation in an SRAM design without sacrificing any circuit performance at all. This scheme has very low area overhead since it uses commonly existing memory BIST circuit for tracking the worst-case silicon speed of the bitlines. It is also highly scalable and therefore suitable for an SRAM compiler that needs to support a wide range of different configurations. Measurement results of 8 manufactured chips of a 2 K-bit SRAM design using TSMC 0.18-$\mu$m CMOS technology demonstrate that it can indeed rescue one originally failing chip, while still warranting correct functionality of all the other seven chips, even under some injected variations in which conventional schemes may fail badly. © 2006 IEEE.