Physics based analysis of a high-performance dual line tunneling TFET with reduced corner effects

Abstract

To improve the DC and analog/HF performance, a novel dual line tunneling based TFET (DLT-ES-TFET) with elevated source and L-shaped pocket is proposed in this manuscript. In DLT-ES-TFET, the elevated top (G1) and extended back (G2) gates overlapping the source region enhance the line tunneling of charge carriers in both vertical and horizontal directions across the source-pocket interface. TCAD-based simulation results reveal that DLT-ES-TFET offers an improvement of ∼47% and ∼54% in average subthreshold swing when it is compared with E-VTSFET and L-TFET, respectively. Furthermore, ON-current in DLT-ES-TFET is also found to be improved by an order of ∼1 as compared to other two devices. In fact, the L-shaped pocket reduces the corner effects caused by the electric filed crowding across source-channel (S-C) interface, which eventually suppresses the OFF-state leakage in the proposed DLT-ES-TFET. Moreover, enhancement in the charge carriers tunneling across S-C interface leads to a huge increment in the transconductance (∼157μs/μm) of DLT-ES-TFET, which further helps in achieving a high cut-off frequency of 12.3 GHz. Next, transient response of DLT-ES-TFET-based resistive load inverter suggests a notable improvement in peak over- and under-shoots along with propagation delay as compared to E-VTSFET and L-TFET. Lastly, interface traps and temperature analysis is also found to be in favor of the proposed DLT-ES-TFET.