A new mechanism for core device failure during CDM ESD events

Abstract

A new mechanism by which core devices may fail during CDM ESD tests has been identified. When CDM test discharges are applied to pins that are directly connected to long on-chip traces, energy may couple inductively to adjacent long lines, thereby bypassing ESD protection elements at the I/o buffers, and causing failure in the non-I/o (core) circuit. Circuit simulation performed on a netlist that was extracted from layout shows that when a 500V CDM stimulus is applied to a pin, this mechanism may generate a voltage at a transistor gate in excess of 20V within the first 100ps. All measured results are in agreement with this proposed mechanism, including failure analysis confirming gate oxide failures at transistors indicated as susceptible by the simulator. © 2006 ESDA.