An enhanced SRAM BISR design with reduced timing penalty

Abstract

Redundancy repair is an effective yield-enhancement technique for memories. There are many previously proposed repair methodologies, such as the popular repair methodology based on the concept of address remapping mechanism achieved by address comparison and address reconfiguration. However, a BISR design with a typical address remapping mechanism usually involves significant timing penalty. Therefore, we propose a new address remapping scheme with a write buffer to reduce the timing penalty. Our experiments show that with the proposed address remapping scheme and redundancy architecture, the timing penalty of our BISR scheme is the same with that of the Built-in Self-Test (BIST) circuit - only one multiplexer delay for both the inputs and outputs. © 2006 IEEE.