Design of SRAM and DRAM Volatile Memories using 45nm Technology for FPGA Architecture

Abstract

The VLSI design of volatile memories SRAM and DRAM has been carried out with 180nm and 45nm CMOS technology for FPGA architecture. The design of the schematics and layout has been carried out using Cadence CAD-Tools. The simulation results of the memory design showing timing analysis and attributes are examined. The power and delay time estimated for the two cases are compared. The results of the VLSI design of the SRAM and DRAM memories show significant reduction in power and delay time for the 45 nm technology compared to 180 nm technology