A 12b 10MS/s 18.9fJ/conversion-step sub-radix-2 SAR ADC

Abstract

This paper presents a 12b SAR ADC with segmented sub-radix-2 DAC and embedded digital calibration. The dither-based calibration with LMS adaptive filter is implemented to track the optimum bit-weights for compensation of DAC mismatch. Mid-threshold comparison switching procedure is proposed to tolerate both-side settling error by equalizing the up and down DAC transition voltage during SAR conversion. The prototyped SAR ADC achieves an FoM of 18.9fJ/conversion-step at 10MS/s and 1V supply. The ADC core and digital calibration part occupies an area of 0.05mm2 and 0.04mm2 in 90nm CMOS, respectively.