Drive Current Enhancement in TFET by Dual Source Region

Abstract

This paper presents tunneling field-effect transistor (TFET) with dual source regions. It explores the physics of drive current enhancement. The novel approach of dual source provides an effective technique for enhancing the drive current. It is found that this structure can offer four tunneling junctions by increasing a source region. Meanwhile, the dual source structure does not influence the excellent features of threshold slope (SS) of TFET. The number of the electrons and holes would be doubled by going through the tunneling junctions on the original basis. The overlap length of gate-source is also studied. The dependence of gate-drain capacitance C gd and gate-source capacitance C gs on gate-to-source voltage V gs and drain-to-source voltage V ds was further investigated. There are simulation setups and methodology used for the dual source TFET (DS-TFET) assessment, including delay time, total energy per operation, and energy-delay product. It is confirmed that the proposed TFET has strong potentials for VLSI.