A 180-GHz Low-Noise Amplifier With Recursive Z-Embedding Technique in 40-nm CMOS

Abstract

This brief presents a high-gain 180-GHz low-noise amplifier with Z-embedding technique. A recursive approach provides an accurate and practical estimation of the maximum available gain with the embedding network while losses of interconnects and embedding components are considered. With the proposed procedure, the essential source embedding capacitance is reduced significantly and therefore practically available. In noise parameters analysis, the equivalent noise resistance is proved to dominate the noise figure deterioration due to the Z-embedding network. The interstage networks are designed to achieve the optimal noise figure. The proposed low-noise amplifier is implemented in a standard 40-nm CMOS technology. This amplifier shows a measured gain of 14.8 dB at 180 GHz, a 3-dB bandwidth of 11 GHz, and a simulated minimum noise figure of 11.0 dB. A low dc power of 23.9 mW is consumed under a 0.9-V supply.