Z-Interference and Z-Disturbance in Vertical Gate-Type 3-D NAND

Abstract

In vertical gate (VG)-type 3-D NAND, reducing either channel polycrystalline silicon (PL) or intersilicon dioxide (OX), or both, allows packing more cells in a fixed volume. However, when programming cells in such an array, the neighbor top/bottom cells suffer significant threshold voltage (Vt) shift due to two unique mechanisms. The first mechanism is the fringing field of the programmed charges (Z-interference), whereas the second one is the degraded inhibited potential affected by the programmed PL channel, which is grounded (Z-disturbance). Z-interference happens before Z-disturbance, so it is more critical to the memory window. Optimizing PL/OX thickness or engineering the PL sidewall profile can balance the constraint of Z-interference and the demand of higher memory density. They are important guidelines when designing VG-type 3-D NAND memory.