A low power and high resolution 2nd order DT sigma-delta modulator for data converters

Abstract

A 2nd order low power and High Resolution discrete time Sigma-Delta modulator presented in this paper for Analog-to-Digital converters (ADC), is developed using CMOS technology. This paper is specifically designed through which it accepts an input signal of frequency 1 KHz, an over sampling ratio (OSR) ≤512 and sampling frequency up to 2MHZ for a second order Sigma-Delta modulator. It is put in to practice in a standard 0.18 µm (180nm) CMOS technology. The design of the sigma-Delta modulator and the simulation of it is done by using CADENCE tools. To form Sigma-Delta modulator this paper essentially elaborates integrator, summer, comparator, D-Latch and Digital-to-Analog (DAC) converters which are integrated together. The key component used in the design is CMOS Operational Amplifier, the OP-AMP open loop gain is 86.8dB, unity gain frequency 5.41 MHz and power consumption is 35.6microwatts. Finally using a ±1.8 v supply voltage a 2nd order Sigma-Delta modulator is realized.