Thru-wafer interconnect for SOI-MEMS 3D wafer-level hermetic packaging

Abstract

This research reports a packaging approach for SOI-MEMS devices using through-wafer vias and anodic bonding technologies. Through-wafer vias are embedded inside the SOI wafers, and are realized using laser drilling and electroplating. These vias provide electrical signal paths to MEMS device, whereas isolate MEMS devices from outer environment. A high-strength hermetic sealing is then achieved after anodic bonding of this through-wafer vias embedded SOI wafer to a Pyrex 7740 glass. Moreover, the packaged SOI-MEMS chip is compatible with the surface mount technology, and performs a superior way for 3D heterogeneous integration. ©2007 IEEE.