Sizing of the CMOS 6T-SRAM cell for NBTI ageing mitigation

Abstract

This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T-staticrandom access memory (6T-SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizingthe nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull-up transistors threatening the cellstability. Once the access transistors are sized for a better hold static noise margin under NBTI, the other transistors of the 6TSRAM cell could be properly sized for improved read stability and write-ability.