Read latency decrease schemes based on check node error rate for 3D NAND flash memories

Abstract

Read retry technique intended to reduce read errors by searching the optimal read voltages and the low density parity check (LDPC) code aimed to correct the reduced read errors are widely used in storage systems to improve reliability of the 3D NAND flash memories. However, the read retry operation and LDPC decoding operation generate long read latency in the data read and recovery process. Here, we propose a check node error rate (CNER) based adaptive-step valley search algorithm (CNER-AVSA) for read retry operations to decrease read latency. CNER-AVSA uses adaptive read voltage moving steps to reduce the read operations required by read retry operations and thus decrease the read latency. To further decrease the read latency, CNER-based invalid-iterations eliminating algorithm (CNER-IEA) used for data recovery is proposed. CNER-IEA decreases the read latency by stopping the read retry operations in advance and eliminating the invalid-iterations in LDPC decoding process. Experimental results show that the proposed CNER-AVSA reduces the raw bit error rate (RBER) of the read errors by up to 78.53 % compared to using default read voltages. The deviations between read voltages searched by CNER-AVSA and the actual truth value of the optimal read voltages are smaller than 25 mV. Implementation results of the CNER-IEA show that the read latency reduces by 43.75 % compared with the conventional data recovery method. Experiment data show that the proposed schemes achieve significant decrease in read errors and read latency.