Bandwidth bottleneck in network-on-chip for high-throughput processors

Abstract

A critical component of high-throughput processors such as GPGPUs is the network-on-chip (NoC) that interconnects the cores andthe memory partitions together. Different NoC architectures forthroughput processors have been proposed but they have oftenbeen based on similar principles as multicore (or CPU) NoC, including emphasis on bisection bandwidth and the traffic pattern. In thiswork, we identify how such prior approaches are not necessarilyapplicable to NoC in throughput processors. We identify how different bandwidth bottlenecks can be created in high-throughputprocessors and argue NoC design for throughput processors needto be re-evaluated.