Hybrid Data Driven Clock Gating and Data Gating Technique for Better Saving Power in ALU RISC-V

Abstract

The study proposes a hybrid data driven clock gating and data gating technique which is applied to ALU in RISC-V. By doing so, the proposed low power technique can improve the power saving efficiency. The proposed low power technique is compared with various low power techniques such as latch-free based clock gating, latch-based clock gating, single data driven clock gating, and single data gating. The results show that the proposed low power ALU saves 46.67% power consumption compared to original ALU. The proposed ALU also shows better saving power than the latch-free based clock gating, latch-based clock gating, sdata driven clock gating, and data gating from 10.84% to 22.23%. The comparison is also implemented on CPU which consists of memory, ALU and control unit. The proposed low power CPU saves 12.11% at least compared to the original CPU. However, the proposed low power CPU is reduced to 15.1% maximum frequency operation compared to the original CPU. The area overhead of the proposed ALU also increased to 33 LUTS (8.2%) and 2 registers (1.6%) compared to the original ALU.