Design of hybrid LUT/MUX FPGA logic architecture for size reduction and performance improvement in FPGA

Abstract

Hybrid configurable logic block architectures for field-programmable gate arrays that contain a blend of LUT's and solidified multiplexers that are assessed towards the objective of higher rationale thickness and diminished region. Innovation mapping advancements that focus on the proposed models are likewise perform inside Xilinx programming. Both for complex rationale square and steering territory while keeping up mapping profundity, the named engineering of this paper examine the rationale size, region and power utilization utilizing Xilinx 14.5.