Memory Testing and Repairing Using MBIST with Complete Programmability

Abstract

Most of the System-on-Chip (SoC) area covered by embedded memories. As these memories are very tightly integrated, consists majority of defects in soc. Detection of such a complex and diverse faults during fabrication is not possible. Hence leads to failure of soc in field. Usage of test algorithms may increase the coverage of complex faults, but unexpected failures can't be covered by these algorithm. Providing possibility of choosing testing algorithms before using in SoC is very important. Programmable BIST approaches, allowing selecting after fabrication a large variety of memory tests, are therefore desirable, but may lead on unacceptable area cost. BIST approaches enabling test algorithm programmability and data background programmability at low area cost have been presented in the past. However, no proposals exist for programming the address sequence used by the test algorithm. In this paper, we extend programmable BIST to complete programmability. This new feature is implemented at low cost by using the memory under test itself to store the desired address sequence and some compact circuitry that enables using this sequence for testing the memory.