Inverter design using junction less GAA tunnel field effect transistor

Abstract

The escalating pressure to defeat the drawbacks of conventional MOSFET such as physical limitations due to its short channel effects has inspired the production of a number of superior materials and device goemetries. In the midst of these novel devices are FinFET, Carbon Nanotube and Nanowires based FETs, having the attributes such as quasi 2-D and 1-D channel geometries for enhanced electrostatics. While a lot of of these modernizations aims only on building up high-performance devices, the making of a roadmap to forecast in-circuit performance combined with large scale integration for these technologies is highly desirable. In this paper we have incorporated Junction less gate all around TFET thus leading to ease of fabrication because of absence of doping concentration gradients for specific regions. In addition low power consumption is obtainable by TFETs as they are less prone to second order effects. The basic inverter circuit has been designed using the device and their performance is examined.