Cryogenic Performance and Modeling of Sub-5nm Fin-Width Bulk FinFETs for Quantum Computing Applications

Abstract

The article discusses characterization and modeling of sub-5nm fin-width bulk FinFETs over temperature. Analysis of the impact of process-induced fin recess defects at cryogenic temperatures reveals that n-FinFET demonstrates superior performance in comparison to p-FinFET. The observation is supported by the extraction of electron and hole mobilities across different temperatures, as well as the extracted values of the channel and series resistance. Increased surface roughness scattering at cryogenic temperatures appears to be the primary cause of performance degradation in p-FinFET. To accurately predict the device behavior at cryogenic temperatures, enhancements are proposed for the BSIM CMG based cryo-compact model. These enhancements accurately capture characteristics of the device over a wide bias range, as well as the trends in threshold voltage, subthreshold swing (SS), and the drain-induced barrier lowering (DIBL) across a broad temperature range. The proposed model is also validated with a standard ring oscillator (RO) simulation, demonstrating its capability for cryo-CMOS circuit design.