Development of a high resolution TDC for implementation in flash-based and anti-fuse FPGAs for aerospace application

Abstract

A high precision, low dead time, large dynamic range time-to-digital (TDC) architecture, suited to be implemented in Actel flash-based and anti-fuse FPGAs, is presented in this paper. A prototype board has been designed with such a TDC implemented in three different industrial grade FPGAs: an anti-fuse FPGA AX500, flash-based FPGAs APA600 and A3PE1500. Test results showed that a time resolution of 225 ps RMS with a 758 ps averaged bin size was obtained for APA600, while 127 ps RMS with 427 ps bin size for A3PE1500. For a TDC in AX500, a RMS of 37 ps with 75 ps bin size was obtained. Thermal tests suggested that the prototype TDCs operate well in a temperature range from -21 C to 71 C with a constant performance after applying a compensation mechanism utilizing the linear relation between TDC bin sizes and ambient temperature. The TDC structure can be directly migrated into space-qualified FPGAs and applied in space experiments. © 1963-2012 IEEE.