Reconfigurable Analog Array for Hardware Security

Abstract

In this paper, a novel field-programmable analog array (FPAA) is proposed to secure the intellectual property (IP) of analog and mixed-signal circuits. A obfuscation technique is developed to efficiently mask the topology of both differential mode and single-ended mode analog circuits. The overhead in performance due to the parasitic impedance of the routing switches is analyzed at the internal nodes connected to the programming switches. Advantages of topology obfuscation include the generation of a large search space, an uncorrelated output response, and flexibility in circuit design. The circuits implemented on the FPAA include an op amp with varying loads, a second order biquad filter, a ring-oscillator, and a frequency divider. For circuits requiring a single configurable analog block (CAB) on the FPAA, the 3 dB bandwidth is maintained around 1 GHz, while circuits requiring multiple CABs operate with frequencies between 200 MHz and 1.5 GHz. The security provided by the FPAA fabric is evaluated on both single CAB implementations as well as multi-CAB circuits. Two attack scenarios are considered, a brute force attack and a topology attack. The multi-CAB circuit provides strong security robustness to both attacks with a minimum search space of 226 for the brute force attack and 210 for the topology attack. The FPAA core is implemented in a 65 nm process with an area of 0.1 mm2.