Low thermal budget processing for sequential 3-D IC fabrication

Abstract

Laser annealing can be used for electrical activation of dopants without excessively heating the material deeper within the work piece. We demonstrate that laser annealing could be used for activating the dopants in the upper levels of an exemplary 3-D integrated circuit structure without affecting the operation of the devices below. We then use a 450 °C low-temperature oxide deposition process for forming the gate oxide and laser annealing for activating the dopants at the source/drain and gate regions to fabricate CMOS transistors. This process can be used to fabricate the transistors on the upper levels of a general 3-D IC structure without affecting the quality of the devices below. © 2007 IEEE.