Integrated Low-Dimensional Semiconductors for Scalable Low-power CMOS Logic

Abstract

Scalable nanoelectronics with energy-efficient logic technology is crucial for next-generation edge devices. Low-dimensional semiconductors, such as transition metal dichalcogenides and single-walled carbon nanotubes (SWCNTs), have tunable properties with reduced short-channel effects. The unique properties of each material can be utilized owing to the heterogeneous integration of multiple semiconducting channels to form complementary metal-oxide-semiconductor (CMOS) logic. However, the integration remains challenging. This study reveals the realization of low static power hetero-CMOS inverters by the integration of n-type monolayer MoS2 and p-type SWCNT networks. The balanced inverter exhibits a large peak gain of ≈67 at a supply voltage of 2 V with the customized design of the wafer-scale synthetic process and channel integration. An ultralow standby power consumption of ≈5 pW and a practical peak gain of ≈7 at a reduced supply voltage of 0.25 V are achieved. A high noise margin (>70%) validates the circuit's tolerance to external noises and the dynamic analysis of the inverting amplifier in push–pull configuration exhibits a large AC gain. This work paves the way toward the wafer-scale integration of low-dimensional materials for low-power nanoelectronics.