On test generation with test vector improvement

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Abstract

We investigate the introduction of a new step, referred to as test vector improvement, into test generation processes. After a fully specified test vector or a partially specified test cube t is generated at an arbitrary iteration of the test generation process, the test vector improvement step modifies t so as to increase the number of yet-undetected target faults that t detects. This is done in this paper using a simulation-based process. We show that even if t was generated using dynamic test compaction heuristics, it is possible to improve t further. When t is partially specified to accommodate test data compression, the test vector improvement step does not change the number of unspecified bits of t. The final result is a smaller test set and/or a higher fault coverage (if the test generation process does not detect all the detectable faults). © 2006 IEEE.

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Pomeranz, I., & Reddy, S. M. (2010). On test generation with test vector improvement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(3), 502–506. https://doi.org/10.1109/TCAD.2010.2041853

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