ExpanderGraph-128: A novel graph-theoretic block cipher with formal security analysis and hardware implementation

Abstract

Lightweight block cipher design has converged toward incremental optimization of established paradigms – substitution-permutation networks, Feistel structures, and ARX constructions – where security derives from algebraic complexity of individual components. We introduce a fundamentally different approach: expander-graph interaction networks, where cryptographic security emerges from sparse structural connectivity rather than component sophistication. Unlike Goldreich-type one-way function constructions that use expander graphs as a single-pass hardness mechanism, our design exploits the expander graph as a diffusion primitive within an iterated, keyed confusion–diffusion framework validated through concrete cryptanalysis. We present ExpanderGraph-128 (EGC128), a 128-bit block cipher instantiating this paradigm through a 20-round balanced Feistel network. Each round applies a 64-bit nonlinear transformation governed by a 3-regular expander graph, where vertices execute identical 4-input Boolean functions on local neighborhoods. Security analysis combines rigorous MILP-based differential bounds, proven optimal via SCIP through 10 rounds, with minimum active Rule-A counts {4, 13, 29, 53, 85, 125, 173, 229, 291, 355} establishing 147.3 bits of provable differential security, conservatively extrapolating to 413 bits for the full 20-round cipher, with formal MILP linear trail bounds (≥2145 distinguisher complexity by conservative extrapolation), related-key analysis proving no free rounds exist for any nonzero key difference, structural attack resistance verified through algebraic degree saturation by round 4 of Fcore and 1800 affine subspace tests finding no invariant structures, and SMT verification. NIST SP 800-22 confirms pseudorandom output quality across 108 bits, with all 15 test categories passing at recommended thresholds. Multi-platform implementation validates practical efficiency with FPGA as the primary target platform: synthesis on Xilinx Artix-7 achieves 261 Mbps throughput at 100 MHz consuming only 380 LUT resources, with the 3-regular graph topology mapping directly to LUT4 primitives and enabling fully parallel single-cycle Fcore evaluation. ARM Cortex-M4F software execution requires 25.8 KB Flash and completes encryption in 1.66 ms, confirming feasibility across the resource-constrained IoT spectrum. Indicative ASIC synthesis on a 45 nm library yields 5.52 kGE from the FPGA-oriented RTL description, representing a conservative upper bound; dedicated ASIC restructuring through bit-serialization would reduce this figure substantially. These results establish expander-based design as a viable methodology for lightweight cryptography, offering a formally grounded design space and opening research directions in adaptive topologies, keyed graph structures, and rigorous security proofs connecting spectral properties to cryptographic resistance.