Network on chip: A survey on router design and algorithms

Abstract

The increase in the applications for the innovative technologies has further increased the computing resources in a single chip. In such scenario, different application desires computing resources to build on a Single Chip. Therefore, interconnection between the IP cores becomes another challenging task. So, this led to the innovation of the Network on Chip as a novel platform those networks inside the System on Chip. There are many disadvantages of the traditional bus based architectures, as it blocks the traffic. The network topologies, routing algorithms and router architectures are the utmost critical part of any network structure. The execution of the system is measured by throughput. The throughput and effectiveness of interconnect depends on the system parameters. In this paper, we are reviewing the previous methods and approaches of routing algorithms and router architectures of NoC.