Multi attribute test pattern optimization for test power minimization in digital circuits

Abstract

Test patterns are the primary bit patterns in need for testing a digital circuitry. Majority of the logical device developed are tested for all functionality before its practical usage. The logical denote and functional complexity has developed new constraint in testing of digital circuit. In developing test patterns for digital test operation, the need of optimal pattern selection are major concern. To develop an optimal test pattern alignment to conserve test power utilization, a new test pattern generation using multi attribute Decision logic and pattern sequencing is proposed. The proposed approach develop a new decision approach in test pattern optimization using the test coverage density and fault test reliability and provide a low power testing approach in digital circuit testing. The simulation result for the proposed system defines the significance of test pattern optimization in power conservation.