Efficient Hardware Accelerator Based on Medium Granularity Dataflow for SpTRSV

Abstract

Sparse triangular solve (SpTRSV) is widely used in various domains. Numerous studies have been conducted using CPUs, GPUs, and specific hardware accelerators, where dataflows can be categorized into coarse and fine granularity. Coarse dataflows offer good spatial locality but suffer from low parallelism, while fine dataflows provide high parallelism but disrupt the spatial structure, leading to increased nodes and poor data reuse. This article proposes a novel hardware accelerator for SpTRSV or SpTRSV-like directed acyclic graphs (DAGs). The accelerator implements a medium granularity dataflow through hardware-software codesign and achieves both excellent spatial locality and high parallelism. In addition, a partial sum caching mechanism is introduced to reduce the blocking frequency of processing elements (PEs), and a reordering algorithm of intranode edges' computation is developed to enhance data reuse. Experimental results on 245 benchmarks with node counts reaching up to 85392 demonstrate that this work achieves average performance improvements of $7.0\times $ (up to $27.8\times $ ) over CPUs and $5.8\times $ (up to $98.8\times $ ) over GPUs. Compared with the state-of-the-art technique (DPU-v2), this work shows a $2.5\times $ (up to $5.9\times $ ) average performance improvement and $1.7\times $ (up to $4.1\times $ ) average energy efficiency enhancement.