Implementation of a 32 – bit RISC processor with floating point unit in FPGA platform

Abstract

With the ever-growing trends in the latest technologies, digital signal processing is one of the known platforms which is used for many applications. RISC processor is the main element in all high-speed digital signal processing applications. The aim is to develop a RISC processor by including a single precision floating point unit in the instruction set along with other instructions and a complex multiplication instruction as it is commonly used in the DSP application. The floating-point unit is written according to the IEEE 754 standard and to introduce Vedic mathematics concept to compare and estimate the performance in terms of delay. The idea is to provide an optimized floating-point arithmetic unit and thereby provide an additional feature for the RISC processor instruction set. By using the Vedic multiplier, the delay is reduced by 55% compared to the normal array multiplier. The entire design is coded in Verilog HDL simulated on Xilinx ISE 14.7 platform.