Full-speed field-programmable memory BIST architecture

Du Xiaogang; Nilanjan Mukherjee; Wu Tung Cheng; Sudhakar M. Reddy

Conference Proceedings

Full-speed field-programmable memory BIST architecture

Proceedings - International Test Conference (2005) 2005 1165-1173

DOI: 10.1109/TEST.2005.1584084

37Citations

5Readers

Get full text

Abstract

A full-speed field-programmable memory BIST controller is proposed. The proposed instruction and architecture designs enable full-speed operation of not only March algorithms but also some non-linear algorithms that are becoming more and more important in modern memory testing, diagnosis, and failure analysis. © 2005 IEEE.

Cite

CITATION STYLE

APA

Xiaogang, D., Mukherjee, N., Cheng, W. T., & Reddy, S. M. (2005). Full-speed field-programmable memory BIST architecture. In Proceedings - International Test Conference (Vol. 2005, pp. 1165–1173). https://doi.org/10.1109/TEST.2005.1584084

Full-speed field-programmable memory BIST architecture

Abstract

Cite

Register to see more suggestions