Approximate Speculative Adder for Low Power VLSI Architectures

Abstract

Approximate Speculative Adder (ASA) for low energy dissipation is proposed in this paper. To enhance the speed of operation pipelining technique is been employed and also to lower the critical path delay utilization of logic gates are also reduced. The structure employs carry look ahead logic for adder implementation. Different configurations have been examined for area and speed. The prime aim lies for lowering the dissipative energy. Also clock skew technique is employed to save the dynamic power consumption. The structure is been analyzed with FPGA and also realized with ASIC. Analysis of results states about the performance of ASA can operate at higher speed than the existing structures. The structure absorbs 5.109 mm2 of chip space. The proposed Approximate Speculative Adder consumes 52.75% of power