HIDEL. A language for hierarchical VLSI design

Abstract

HIDEL (HIerarchical DEscription Language) is a new language for structural description of hardware systems. The use of HIDEL allows a modular and hierarchical description of a hardware system. HIDEL can be integrated with a data model, called the Hierarchical Hypergraph with Ports (HHP), which provides a graph-based description of a VLSI object at different levels of specification. The possibility of extending the HIDEL-HHP environment with functional description for simulation is also investigated.