Contemporary design of logic BIST using non linear S-box function as PPRG

Abstract

Built-In Self-Test is a design for testability (DFT) method used for testing integrated circuits. It provides to test both logic circuits and memory cores in a system. For testing a logic circuit we need test vectors. This paper describes about Pseudo pattern random number generator used in BIST scheme to generate test patterns. In some applications requirement of test patterns will be more in that case a simple LFSR based LBIST is unsatisfactory. In this paper an alternative method is used for the generation of more test patterns. This can be achieved by a non linear function that is Substitution Box in combination with LFSR known as S-box based random number source. This feature empowers it for utilizing in Logic BIST and Memory BIST architecture. Functionality of LFSR, S-box based random number generator and LBIST structures are verified using Xilinx Vivado 18.2 tool.