Approaches to multi-level sequential logic synthesis

Abstract

The author presents approaches to multilevel sequential logic synthesis-algorithms and techniques for the area and performance optimization of interconnected finite-state machine descriptions. New techniques are presented for the exploitation of sequential don't cares in arbitrary, interconnected sequential machine structures. Exploiting these don't care sequences can result in significant improvements in area and performance. The author addresses the problem of migrating logic across state machine boundaries so as to make particular machines less complex at the possible expense of making others more complex. This can be useful from both an area and a performance point of view. The author presents novel optimization algorithms that incrementally modify state machine structures across latch boundaries. He discusses the use of more global state machine decomposition and factorization algorithms for area optimization. Finally, he presents experimental results obtained using these algorithms on sequential circuits.