Comparative evaluation of Tunnel-FET ultra-low voltage SRAM bitcell and impact of variations

Abstract

In this paper, the advantages and the challenges posed by Tunnel FETs (TFETs) are studied in the context of ultra-low voltage SRAM bitcells operating below 500 mV. A comparative analysis of TFETs, SOI and bulk CMOS in 32 nm technology is performed through device- (TCAD) and circuit-level (VerilogA) simulations. Sensitivity to the key device parameters is analyzed to quantitatively evaluate the impact of the corresponding variations. Interestingly, our analysis shows that TFETs are less sensitive than SOI/bulk to device parameters that are affected by the gate pitch. Hence, TFETs can help mitigate the printability issues in 32-nm technologies and beyond.