Register Allocation for Compressed ISAs in LLVM

Abstract

We present an adaptation to the LLVM greedy register allocator to improve code density for compressed RISC ISAs. Many RISC architectures have extensions defining smaller encodings for common instructions, typically 16 rather than 32 bits wide. However, these instructions typically cannot access all the processor's registers, and might only have room to specify two registers even for binary operations. When a register allocator is aware of these restrictions, it can analyze the compressibility of instructions and assign registers in such a way that as many instructions as possible can use the smaller encoding. We adapted four aspects of the LLVM greedy register allocator in order to enable more compressed instructions: 1. Prioritize virtual registers with many potentially compressible instructions for earlier assignment. 2. Select registers so that the number of compressed instructions is maximized. 3. Take compressibility into account when deciding which virtual registers to spill. 4. Weigh more register copies against more opportunity for compression. We evaluate our techniques using LLVM's RISC-V backend. In the SPEC2000 and SPEC2006 benchmarks, our register allocator produces between 0.42 % and 6.52 % smaller binaries. In the geometric mean, binaries become 1.93 % smaller. We see especially large improvements on some floating-point-heavy benchmarks. Binaries compiled for better compression show changes in their execution time of at most ± 1.5 %. We analyze these against LLVM's spilling metrics, and conclude that the effect is probably not systemic but a random fluctuation in the register allocation heuristic.